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    • 专利摘要:
    In generating the inverted input signal input to the level shifter in the inverter section, a voltage VHL for giving a high level output voltage of the inverter section is generated by resistance division from the power supply voltages VHH and VLL in the voltage divider section. do. This makes it possible to provide a level shift circuit which realizes a reduction in the number of input terminals and a low power consumption by a simple circuit configuration.
    公开号:KR20010100766A
    申请号:KR1020010002937
    申请日:2001-01-18
    公开日:2001-11-14
    发明作者:사카이타모츠；오가와야수유키
    申请人:마찌다 가쯔히꼬；샤프 가부시키가이샤；
    IPC主号:
    专利说明:

    LEVEL SHIFT CIRCUIT AND IMAGE DISPLAY DEVICE}
    [12] The present invention relates to a level shift circuit, and more particularly, to a level shift circuit operated by an input signal and an inverted input signal.
    [13] 10 shows an example of the configuration of a conventional level shift circuit. The level shift unit 101 in the level shift circuit is composed of four MOS transistors, that is, PMOS transistors P81 and P82 and NMOS transistors N81 and N82.
    [14] The PMOS transistor P81 and the NMOS transistor N81 are connected in series through the terminals of the inverted output signal OUT B between the power supply voltages VHH and VLL. In the same manner, the PMOS transistor P82 and the NMOS transistor N82 are also connected in series between the power supply voltages VHH and VLL through the terminals of the output signal OUT. The output signal OUT may also be an input to the gate of the PMOS transistor P81, and the inverted output signal OUT B may also serve as an input to the gate of the PMOS transistor P82.
    [15] The input signal IN is input to the gate of the NMOS transistor N81. On the other hand, the inverting input signal IN B which inverts the said input signal IN by the inverter part 102 is input to the gate of the NMOS transistor N82. The inverter section 102 has a configuration in which the PMOS transistor P83 and the NMOS transistor N83 are connected in series between the power supply voltages VHL and VLL.
    [16] In the level shift circuit having the above configuration, when the low level (voltage VL) signal is input as the input signal 1N, the NMOS transistor N81 is turned off. The input signal IN is also applied to the gates of the PMOS transistor P83 and the NMOS transistor N83 of the inverter unit 102, whereby the PMOS transistor P83 is turned on and the NMOS transistor N83 is turned off. do. That is, the output from the inverter unit 102 forms the output voltage of VHL in the state where only the PMOS transistor P83 is turned on.
    [17] Therefore, the inversion input signal IN B of the high level (voltage VHL) in which the input signal IN is inverted is input to the NMOS transistor N82. For this reason, the level of the output signal OUT becomes the VLL level on the drain side of the NMOS transistor N82. The PMOS transistor P81 to which the output signal OUT is connected to the gate is turned on because the gate level becomes VLL, and the level of the inverted output signal OUT B becomes the VHH level on the drain side thereof. The PMOS transistor P82 to which the inverted output signal OUT B of this VHH level becomes a gate input is turned off.
    [18] As described above, in the level shift circuit, when the input signal IN of the low level (voltage VL) is input, the output signal OUT is stabilized at the VLL level and the inverted output signal OUT B is at the VHH level. On the contrary, when the input signal IN becomes the high level (voltage VH), the output signal OUT is stabilized at the VHH level and the inverted output signal OUT B is at the VLL level.
    [19] In the structure of FIG. 10, the inverter unit 102 is used to obtain the inverting input signal IN B input to the gate of the NMOS transistor N82. However, as shown in FIG. The same level shift operation may be performed by removing the signal and inputting the signal IN B from the outside.
    [20] However, in the conventional level shift circuit shown in FIG. 10, in addition to the power supply voltages VHH and VLL for the circuit after the level shift, the power supply voltage VHL for the inverter section 102 which generates an inverted input signal before the level shift. ) Is required. These power supplies need to be input externally to the level shift circuit, resulting in an increase in the number of terminals of the circuit.
    [21] In the level shift circuit shown in Fig. 11, the inverting input signal IN B is generated by an external circuit and inputted to the level shift circuit, but in this case, most of the signals that need to be input from the outside convert the inverted signal thereof. This necessitates an increase in the number of terminals.
    [22] It is an object of the present invention to provide a level shift circuit and an image display apparatus which realize a reduction in the number of input terminals and reduction in power consumption by a simple circuit configuration.
    [23] In order to achieve the above object, the level shift circuit according to the present invention comprises: an input signal and an inverting input signal inverting the high / low of the input signal are input, and a first voltage and a second power source voltage, which are high power voltages; A level shifter means connected to the voltage and switching the first voltage and the second voltage in response to the high / low of the input signal and the inverted input signal; A third voltage for providing an output level corresponding to one of the input signal, one of the first voltage and the second voltage, and a low level or a high level of the inverted input signal is input, and to a high / low level of the input signal. Inverting input signal generating means for generating an inverting input signal inverting the input signal by switching the output voltage level accordingly; And voltage dividing means for dividing and extracting the third voltage between the first and second voltages.
    [24] When an input signal and an inverted input signal inverted thereof are required as the input signal of the level shifter means, the low level or the high level of the inverted input signal in addition to the first and second voltages that give the high level and the low level of the output signal. A third voltage is required that gives an output level corresponding to
    [25] This third voltage is conventionally supplied as a power supply voltage outside of the level shift circuit, and thus requires a terminal. In the above configuration, the third voltage is obtained from the first and second voltages in the voltage dividing means. Produced by partial pressure. For this reason, the terminal for inputting a 3rd voltage becomes unnecessary, and the number of terminals in a level shift circuit can be reduced.
    [26] In addition, the level shift circuit of the present invention internally generates an inverted input signal that is an inverted signal with respect to an input signal input from the outside, and shifts the input signal level according to the high / low of the input signal and the inverted input signal. A level shift circuit for outputting a voltage is generated by resistance division from a power supply voltage for giving an output level of an output signal after level shifting.
    [27] In the case where the input signal and the inverted input signal are used in the conventional level shift circuit, the inverted input signal is considered to be input from the outside as in the input signal and two cases generated internally. When the inverting input signal is input from the outside, a corresponding input terminal is required in the level shift circuit. In addition, even when the inverted input signal is generated internally, a voltage for giving a low or high level output level of the inverted input signal is required in addition to a power supply voltage for giving an output level of the output signal after level shifting. The terminal for providing this voltage is needed.
    [28] In contrast, in the configuration of the level shift circuit of the present invention, the voltage giving the low or high level output level of the inverted input signal is generated by resistance division from the power supply voltage giving the output level of the output signal after the level shift. do. In other words, in the level shift circuit, only a terminal for inputting a power supply voltage that gives an output level of the output signal after the level shift is sufficient, so that the number of terminals can be reduced.
    [29] The image display device of the present invention is an active matrix image display device in which pixels for displaying are provided in a matrix, and the data signal driving circuit and the scanning signal driving circuit include the level shift circuit. have.
    [30] In the image display apparatus, the number of terminals in the data signal driving circuit and the scanning signal driving circuit can be reduced.
    [31] Other objects, features, and advantages of the present invention will become more clearly understood from the following description with reference to the accompanying drawings.
    [1] 1 is a circuit diagram showing a configuration of a level shift circuit, showing an embodiment of the present invention;
    [2] 2 (a) and 2 (b) are circuit diagrams showing an example of the configuration when the voltage divider of the level shift circuit is composed of transistors, and FIG. 2 (a) shows an example using an NMOS transistor, and FIG. 2 (b) shows a PMOS. A circuit diagram showing an example using a transistor,
    [3] 3 (a) and 3 (b) are circuit diagrams showing another example of the configuration when the voltage divider of the level shift circuit is constituted by transistors. FIG. 3 (a) shows an example using an NMOS transistor, and FIG. A circuit diagram showing an example using a PMOS transistor,
    [4] 4 is a circuit diagram showing another configuration example in the case where the voltage divider of the level shift circuit is constituted by a transistor;
    [5] Fig. 5 shows a modification of the level shift circuit according to the present invention, which is a circuit diagram showing the configuration of a level shift circuit for performing a low-level shift.
    [6] 6 (a) and 6 (b) are graphs showing the relationship between the threshold value and the divided voltage potential of a polysilicon transistor which is a PMOS transistor, and FIG. 6 (a) shows the input of the gate voltages of VLL (low level) and VLL + 5V ( (B) is a circuit diagram showing a case where the gate voltage input is switched between VLL (low level) and VLL + 6V (high level).
    [7] 7 (a) and 7 (b) are graphs showing the relationship between the threshold value and the voltage divider potential of a polysilicon transistor which is an NMOS transistor, and FIG. 7 (a) shows the input of the gate voltages of VHH (high level) and VHH-5V ( 7 (b) is a graph showing a case where the input of the gate voltage is switched between VHH (high level) and VHH-6V (low level),
    [8] 8 is a graph showing the relationship between the total resistance value (divisional resistance value) of the resistance in the voltage divider and the operating frequency of the level shift circuit;
    [9] 9 is an explanatory diagram showing a configuration example of an image display apparatus using the level shift circuit;
    [10] 10 is a circuit diagram showing a configuration of a conventional level shift circuit, and
    [11] Fig. 11 is a circuit diagram showing the structure of another conventional level shift circuit.
    [32] 1 shows an example of the configuration of a level shift circuit according to the present embodiment. The level shifter (level shifter means) 1 in the level shift circuit is composed of four MOS transistors, that is, PMOS transistors P11 and P12 and NMOS transistors N1 and N12.
    [33] The PMOS transistor P11 and the NMOS transistor N11 are connected in series between the power supply voltages VHH and VLL through the terminals of the inverted output signal OUT B. In the same manner, the PMOS transistor P12 and the NMOS transistor N12 are also connected in series between the power supply voltages VHH and VLL through the terminals of the output signal OUT. The output signal OUT also serves as an input to the gate of the PMOS transistor P11, and the inverted output signal OUT B also serves as an input to the gate of the PMOS transistor P12.
    [34] The input signal IN is input to the gate of the NMOS transistor N11. On the other hand, the inverting input signal IN B which inverts the said input signal IN by the inverter part (inverting input signal generation means) 2 is input into the gate of the NMOS transistor N12. In the inverter section 2, the PMOS transistor P13 and the NMOS transistor N13 are connected in series between the power supply voltages VHL and VLL.
    [35] In the level shift circuit having the above configuration, when the low level (voltage VL) signal is input as the input signal IN, the NMOS transistor N1 is turned off. The input signal IN is also applied to the gates of the PMOS transistor P13 and the NMOS transistor N13 of the inverter unit 2 so that the PMOS transistor P13 is turned on and the NMOS transistor N13 is turned off. That is, the output from the inverter section 2 becomes the output voltage of VHL by turning on only the PMOS transistor P13.
    [36] With this configuration, the inverting input signal IN B of the high level (voltage VHL) in which the input signal IN is inverted is input to the NMOS transistor N12, and the NMOS transistor N12 is turned on. In the drain of the NMOS transistor N12, the level of the output signal OUT becomes the VLL level. The PMOS transistor P11 to which this output signal OUT is connected to the gate is turned on because the gate level becomes VLL, and at the drain thereof, the level of the inverted output signal OUT B becomes the VHH level. The PMOS transistor P12 to which the inverted output signal OUT B of this VHH level becomes a gate input is turned off. In the description of the present embodiment, on the other hand, for the NMOS transistor, the low voltage side is the source and the high voltage side is the drain, and for the PM0S transistor, the high voltage side is the source and the low voltage side is the drain.
    [37] In this way, the input signal IN of the low level (voltage VL) is input in the level shift circuit. In this case, the output signal OUT is stabilized at the VLL level and the inverted output signal OUT B is at the VHH level. On the contrary, when the input signal IN is at the high level (voltage VH), the output signal OUT is set at the VHH level and the inverted output signal OUT B is set at the VLL level and stabilized. In general, in the input signal IN, the high level voltage VH is coincident with the voltage VHL, and the low level voltage VL is coincident with the voltage VLL.
    [38] Here, in the inverter section 2 constituted by the PMOS transistor P13 and the NMOS transistor N13, the voltage VHL (third voltage) for giving the output on the high level side is the power supply voltage VHH (first Voltage) and VLL (second voltage) are generated by dividing by a voltage dividing section (dividing means) 3. The voltage divider 3 is formed by connecting the resistors R1 and R12 in series between the power supply voltages VHH and VLL, and divides the voltages VHH and VLL by drawing voltages between the resistors. VHL).
    [39] The voltage VHL generated by the resistance divided voltage is at a level substantially equal to the high level voltage VH of the input signal IN. However, if the voltage shifter 1 is capable of operating, the voltage VHL is different from the voltage VH. Value can be set. More specifically, the value of VHL is determined by the threshold voltage of the NMOS transistor N12 serving as the gate input.
    [40] The value of VHL is determined by the ratio of the resistance values of the resistors R1 and R12, but the value of the normal current at this time is determined by the sum of the resistance values, and this value can be changed according to the operating speed of each signal. In the case where the level shift circuit operates with a high frequency signal, if the input signal IN is a low level voltage VL, the inverting input signal IN B becomes a high level voltage VHL, and thus VHL in a short time. Since a current capable of outputting the level is required, the total resistance of the resistors R1 and R12 is reduced.
    [41] On the contrary, when using a signal that is hardly influenced by the timing of the signal as the low frequency, it is possible to greatly reduce the steady current by increasing the total resistance of the resistors R1 and R12. For this reason, when a low frequency signal is used, the level shift circuit of this embodiment can not only reduce the number of input terminals, but also greatly contribute to lower power consumption.
    [42] The resistors R1 and R12 in the voltage divider 3 are preferably made of a semiconductor device. In this case, the resistances can be stably provided in a small area. Further, even if the area is increased, it can overlap the lower surface or the surface of the metal wiring, so that free space such as the wiring portion can be effectively used, and space of the circuit can be saved. The semiconductor element may be composed of an n-type semiconductor (for example, silicon doped with phosphorus as a donor) or a p-type semiconductor (for example, silicon doped with boron as an acceptor).
    [43] Each resistor in the voltage divider 3 may be constituted by a MOS transistor. FIG. 2A shows an example using an NMOS transistor, but in this case, NMOS transistors N21, N22, and N23 having the same channel length are connected in series between power supplies VHH and VLL, and each NMOS transistor N21, N22, The gate of N23 is connected to the power supply voltage VHH. The output voltage VHL is extracted at the connections of the NMOS transistors N22 and N23.
    [44] In addition, the channel length of each NMOS transistor can be set to a different size so that a desired voltage can be obtained.
    [45] Here, the number and output power extraction points of the NMOS transistor are not particularly limited, but need to be adjusted according to the characteristics of the transistor to obtain a desired voltage and current. As shown in Fig. 2 (b), it is possible to configure the PM0S transistor instead of the NMOS transistor. In this case, the gates of the respective PM0S transistors P31, P32, and P33 are connected to the power supply voltage VLL.
    [46] In the configuration of the voltage divider 3 shown in Fig. 2A, the gates of the NMOS transistors connected in series between the power supply voltages VHH and VLL are all connected to the high power supply voltage VHH. The gate of each NMOS transistor can be connected to its own drain. That is, as shown in FIG. 3A, the gate of the NMOS transistor N41 is connected to the power supply VHH, the gate of the NMOS transistor N42 is x42, and the gate of the NMOS transistor N43 is connected to the voltage divider 3. It can be connected to the output voltage VHL.
    [47] As shown in Fig. 3B, even when a PMOS transistor is used instead of an NMOS transistor, the gate of each PM0S transistor can be connected to its own drain. In this case, the gate of the PM0S transistor P51 can be connected to x51, the gate of the PMOS transistor P52 to the output voltage VHL, and the gate of the PMOS transistor P53 to the low power supply voltage VLL.
    [48] In the case where the PMOS transistors are used as the resistors connected in series between the power supply units VHH and VLL in the voltage divider 3, as shown in FIG. 4, they are input to the gates of these PMOS transistors P61, P62, and P63. The signal IN can be connected. In this case, when the input signal IN is at the low level VL, the PMOS transistors P61, P62, P63 are turned on, and the voltage VHL is supplied to the high power supply side VHL of the inverter unit 2.
    [49] On the other hand, in the above configuration, when the input signal IN is at the high level VH, the voltage applied between the gate and the source of each transistor is smaller than at the low level, and the resistance between the source and the drain is high, thereby increasing the power supply ( Since the current flowing from the VHH) to the power supply VLL becomes small, the current can be controlled and low power consumption is realized.
    [50] In addition, each resistance in the voltage divider 3 may be provided by a combination of the above-described resistance generating method.
    [51] As described above, the level shift circuit outputs a higher level output signal OUT when a high level input signal IN is input. That is, the level shift circuit is configured to shift the input signal IN to a high level, but even in the case of a level shift circuit for shifting the input signal to a low level, the present invention can be realized by adjusting the output voltage at the voltage divider. Can be. Fig. 5 shows an example of the configuration of a level shift circuit for performing such a low level shift.
    [52] In the case of the level shift circuit configured to shift the input signal to the low level, the inverter unit 2 'which receives the input signal IN and outputs the inverted input signal IN B to the level shifter 1' The voltage VHL after the voltage dividing by the voltage divider 3 'is input to the source side of the NMOS transistor N73, and the power supply voltage VHH on the high voltage side is connected to the source side of the PMOS transistor P73. Thus, a level shift circuit for shifting to a low level can be configured.
    [53] In the level shift circuit according to the present embodiment, the level shifter (level shifter 1 or level shifter 1 ') and the inverter (inverter 2 or inverter 2') are made of polysilicon film. It is comprised by the formed MOS transistor. In addition, the voltage divider (the voltage divider 3 or the voltage divider 3 ') is also formed of one of an n-type semiconductor, a p-type semiconductor, an NMOS transistor, and a PMOS transistor formed of polysilicon to form a level shifter and an inverter. It is composed of a film such as a silicon film.
    [54] In this manner, by dividing the voltage divider into a polysilicon film like the level shifter and the inverter, the entirety of the level shift circuit can be formed on the same substrate, and it is simpler to divide the voltage using a resistor or the like from the outside. With this configuration, the level shift circuit can be manufactured.
    [55] However, since the M0S transistor formed of the polysilicon film has a large threshold value difference and its operable range is limited, it is necessary to specify the divided voltage VHL. More specifically, in a MOS transistor formed of a polysilicon film, a gap occurs in a range of about 2 to 3 V with respect to the designed threshold value. When the design value is 3 V in an NMOS transistor, the gap is about 0 to 6 V and a design value in a PMOS transistor. If it is set to -3V, the difference is about -6 to 0V.
    [56] For this reason, in the level shift circuit composed of the polysilicon transistor having the above characteristics, the practical range of the level shift circuit is broadened by appropriately designating the voltage VHL with respect to the threshold gap of the polysilicon transistor generated according to the lot. It is preferable to set.
    [57] In the level shift circuit of the configuration shown in Fig. 1 for shifting the input voltage to a high level, the voltage is changed between VHH-VLL to about 10 to 20V and input voltage is changed to a range between VLL and VLL + 5V. The operating range of the PMOS transistor P13 is shown in Fig. 6A. In this figure, the horizontal axis represents the threshold of the PMOS transistor, and the vertical axis represents the voltage VHL-VLL obtained by subtracting the voltage VLL from the voltage VHL generated by resistance division of the power supply voltages VHH and VLL.
    [58] In the level shift circuit of FIG. 1, the voltage VHL generated by the voltage divider 3 is connected to the source of the PMOS transistor P13, and the relationship between the threshold value of the PMOS transistor P13 and the voltage VHL. The operation range of the PMOS transistor P13 is limited by this. More specifically, in the PMOS transistor P13, in the case of (gate input voltage)-(source input voltage) <(threshold), the PMOS transistor P13 is turned on and (gate input voltage)-(source input voltage). In the case of)> (threshold).
    [59] For example, when the threshold is -3V, when the input IN is at the low level VLL, the voltage VLL is applied to the gate of the PMOS transistor P13. At this time, in order for the PMOS transistor P13 to be turned on by the low level input, the source input voltage, that is, the voltage VHL must be greater than VLL + 3V. In practice, the voltage VHL should be set above VLL + 4V with a margin of 1V to more reliably turn on.
    [60] On the other hand, when the input IN is at the high level (VLL + 5V), the voltage VLL + 5V is applied to the gate of the PMOS transistor P13. At this time, the voltage VHL should be set to VLL + 5 + 3V or less so that the PMOS transistor P13 is turned off by the high level input. On the other hand, when the transistor is off, since the current hardly flows when the gate voltage is less than or equal to the threshold value, the same margin as on (1 V margin) is not required.
    [61] For this reason, in the level shift circuit having the configuration shown in Fig. 1, if the threshold of the PM0S transistor P13 is -3V, the voltage VHL becomes a voltage between VLL + 4V and VLL + 8V, and the voltage between VHL and VLL. Has a driving margin of about 4 to 8V.
    [62] At this time, the threshold voltage of the NMOS transistor does not need to be specifically designated as long as the level shifter operates. More specifically, it is operable if the voltage between the high level and the low level of the input is set to about -1V or less.
    [63] Further, even when the threshold value of the PMOS transistor P13 has a value other than -3V, the driving margin of the voltage between VHL and VLL is the same as that of the threshold value -3V as shown in Fig. 6A. Has a driving margin. Accordingly, the PMOS transistor P13 has an operable range indicated by oblique lines in the figure.
    [64] Here, as described above, in the PMOS transistor P13 having the design value of the threshold value of -3V, there is a gap of the threshold value according to the lot, and the gap is in the range of -6 to 0V, but the gap is not equal, and the designed threshold value is The frequency of occurrence of -3V is the highest. As the difference between the design value -3V and the threshold becomes larger, the frequency of occurrence of the corresponding threshold becomes lower.
    [65] In order to stably drive the level shift circuit with respect to the threshold gap of the PMOS transistor P13, the voltage VHL serving as the source input of the PMOS transistor P13 is wider than the operable range, and- It is desirable to specify a value that can be covered by a range close to the design value of 3V.
    [66] The case illustrated in FIG. 6 (a) will be described below in more detail. That is, for the PMOS transistor P13 having a threshold value of -3V as designed, stable operation can be performed when the voltage between VHL and VLL is set to a given value in the range of 4 to 8V. However, when the voltage between VHL and VLL is designated as 4V or 8V, in order for the PMOS transistor P13 to operate stably as shown in Fig. 6A, the threshold is -6 to -3V or-. It is necessary to be in the range of 3 to 0V, and therefore the width of the threshold range allowable in the PMOS transistor P13 is 3V.
    [67] On the other hand, when the voltage between VHL and VLL is designated as one of 5V, 6V, and 7V, the thresholds are -6 to -2V, -5 to -1V, or -4 to 1 in order for the PMOS transistor P13 to operate stably. It is necessary to be in the range of 0V, so the width of the threshold range allowable in the PMOS transistor P13 is 4V. In this way, by specifying the voltage between VHL and VLL (that is, specifying the voltage VHL), the threshold range allowable in the PMOS transistor P13 can be expanded.
    [68] In addition, when the voltage between VHL and VLL is designated as one of 5V, 6V, and 7V, the width of the allowable threshold range in the PMOS transistor P13 is 4V in any case, of which the threshold range is the most at the design threshold -3V. The closest case is when the voltage between VHL and VLL is specified as 6V. In other words, when the voltage between VHL and VLL is designated as 6 V, the frequency of occurrence of the threshold within the allowable threshold range in the PMOS transistor P13 is the highest, and the yield of the level shift circuit which can obtain stable operation is improved. , The most preferable configuration.
    [69] On the other hand, while the above description discloses a specific example based on the graph of Fig. 6 (a), the designation of the voltage (VHL) in the above consideration is the driving margin at the design threshold (which is expected to be the most frequent) of the PMOS transistor. It is preferable to set it to an intermediate value. In the above example, the driving margin of the design threshold of the PMOS transistor P13 indicates that the voltage between VHL and VLL is 4 to 8V, and the intermediate value of 6V is the most desirable result.
    [70] In addition, the high level of the input voltage to the gate of the PMOS transistor P13 is not specified as VLL + 5V as described above, but may be VLL + 5V or more. When the high level of the input voltage rises above VLL + 5V, the operating margin of the voltage VHL relative to the PMOS transistor threshold voltage increases. More specifically, as shown in Fig. 6 (b), the upper limit of the margin of the voltage VHL is increased by 1V by increasing the high level of the input voltage by 1V to VLL + 6V. Margin is increased by 2V. In this manner, the margin of the upper limit of the voltage VHL can be secured in proportion to the increase amount of the high level input voltage.
    [71] In this manner, by increasing the high level of the gate input voltage of the PMOS transistor P13, the relationship between the voltage VHL and the PMOS transistor P13 is affected, so that the upper limit of the voltage margin of the voltage VHL is increased. Will increase. At this time, if the low level input voltage is not changed, the lower limit of the voltage margin does not change, and the driving margin for the entire threshold is increased.
    [72] In the example shown in Fig. 6B, the design threshold of the PMOS transistor P13 is -3V, and the driving margin of the PMOS transistor P13 having a threshold of -3V is 4 as the voltage between VHL and VLL. 9V. At this time, the intermediate value of the driving margin is 6.5V, and the voltage VHL is designated as VLL + 6.5V. In addition, when the voltage VHL is designated as VLL + 6.5V, the allowable threshold range in the PMOS transistor P13 is set to -0.5 to -5.5V, has a width of 5V, and thus is shown in Fig. 6A. In comparison, the width of the allowable threshold range is increased by 1V.
    [73] In the above description, an example is described in the level shift circuit of the configuration of FIG. 1 in which the input voltage is shifted to the high level. However, even in the level shift circuit of the configuration in which the input voltage is shifted to the low level, In a level shift circuit having a configuration shifted to a low level in a silicon transistor, the practical range of the level shift circuit can be extended by appropriately designating the voltage VHL with respect to the threshold gap of the silicon transistor (NMOS transistor).
    [74] In the level shift circuit of the configuration of FIG. 5 for shifting the input voltage to the low level, the NMOS transistor is set under an input condition in which the voltage between VHH and VLL is set to about 10 to 20 V, and the input voltage is switched between VLL-5V and VLL. The operating range of N73 is shown in Fig. 7A. In this figure, the horizontal axis shows the threshold value of the NMOS transistor, and the vertical axis shows the voltage between VHH and VHL obtained by subtracting the voltage VHH from the voltage VHL generated by resistance division of the power supply voltages VHH and VLL. .
    [75] In the level shift circuit of FIG. 5, the voltage VHL generated by the voltage divider 3 ′ is connected to the source of the NMOS transistor N73, and the threshold value and voltage VHL of the NMOS transistor N73 are adjusted. By this relationship, the operating range of the NMOS transistor N73 is limited.
    [76] Here, for example, when the threshold value is 3V, when the input IN is at the low level (VHH-5V), the voltage VHH-5V is applied to the gate of the NMOS transistor N73. At this time, in order for the NMOS transistor N73 to be turned off by the low level input, the source input voltage, that is, the voltage VHL, needs to be VHH-5-3V (that is, VHH-8V or more).
    [77] On the other hand, when the input IN is at the high level VHH, the voltage VHH is applied to the gate of the NMOS transistor N73. At this time, in order for the NMOS transistor N73 to be turned on by the high level input, the voltage VHL must be equal to or less than VHH-3V. In practice, the voltage VHL needs to be less than or equal to VHH-4V so as to be surely turned on.
    [78] For this reason, in the level shift circuit of FIG. 5, if the threshold value of the NMOS transistor N73 is 3V, the voltage VHL is set to a voltage between VHH-4V and VHH-8V, and the voltage between VHH and VHL Has a driving margin of about 4 to 8V. At this time, the threshold voltage of the PM0S transistor need not be specifically designated as long as the level shifter operates. More specifically, it is operable if the absolute value of the threshold of the PM0S transistor is set to about −1 V or less, which is the voltage between the high and low levels of the input.
    [79] Also, even when the threshold value of the NMOS transistor N73 has a value other than 3V, the driving margin of the voltage between VHH and VHL is the same as that of the threshold value 3V as shown in Fig. 7A. It is set to have a margin. Thus, the NMOS transistor N73 may have an operable range indicated by oblique lines in the figure.
    [80] On the other hand, even in a level shift circuit having a configuration in which the input voltage is shifted to a low level, the designation of the voltage VHL is preferably set to the intermediate value of the driving margin of the design threshold of the NMOS transistor (which is expected to be the most frequent). . Therefore, in the above example based on the graph of Fig. 7A, the driving margin of the design threshold of the NMOS transistor N73 (here, 3V) is 4 to 8V between VHH and VHL, with 6V being the intermediate value most preferred. Do.
    [81] In addition, the low level of the input voltage to the gate of the NMOS transistor N73 is not specified as VHH-5V as described above, but may be set to VHH-5V or less. If the low level of the input voltage is set above VHH-5V, the operating margin of the voltage VHL relative to the NMOS transistor threshold voltage increases. More specifically, as shown in FIG. 7B, the upper limit of the margin of the voltage VHL is increased by 1 V by decreasing the low level of the input voltage by 1 V to VHH-6V, and similarly, the margin of the voltage VHL is decreased by 2V. This increases by 2V. In this manner, the margin of the upper limit of the voltage VHL can be secured in proportion to the increase amount of the low-level input voltage.
    [82] In this manner, by reducing the low level of the gate input voltage of the NMOS transistor N73, the relationship between the voltage VHL and the NMOS transistor N73 is influenced, and thus the upper limit of the voltage margin of the voltage VHL. This increases. At this time, if the high level input voltage is not changed, the lower limit voltage margin does not change, and the driving margin for the entire threshold value increases.
    [83] In the case shown in Fig. 7B, the design threshold of the NMOS transistor N73 is 3V, and the driving margin of the NMOS transistor N73 having a threshold of 3V is 4 to 9V as the voltage between VHH and VHL. At this time, the intermediate value of the driving margin is 6.5V, and the voltage VHL is designated VHH-6.5V. In addition, when the voltage VHL is designated as VHH-6.5V, the threshold range allowable in the NMOS transistor N73 is 0.5 to 5.5V and has a width of 5V. Thus, as compared with the case shown in Fig. 7A, the width of the allowable threshold range is increased by 1V.
    [84] Further, in the level shift circuit according to the present embodiment, the operable frequency characteristic can be determined by the total resistance value (hereinafter, divided voltage resistance value) of the resistances of the voltage dividers 3 and 3 '. 8 shows the relationship between the divided resistance value and the operable frequency of the level shift circuit. In this figure, the area indicated by the oblique line is the operable area of the level shift circuit. As shown in this figure, the smaller the voltage divider resistance, the wider the operating frequency at which the level shift circuit can operate, but the larger the voltage divider resistance, the smaller the operating frequency at which the level shift circuit can be operated.
    [85] For this reason, the level shift circuit of the present invention is effective especially when switching the DC potential which does not depend on the operating frequency, and it is possible to realize lower power consumption by increasing the resistance value.
    [86] As an example of the practical use of the level shift circuit, in an active matrix type image display apparatus, the circuit uses a switching operation using DC, such as when switching modes of switching a data signal driving circuit or a scanning signal driving circuit. It can be used to generate a signal that executes. Therefore, the voltage dividing resistance value in the voltage dividing unit can be made as large as possible, and further lower power consumption can be realized.
    [87] In the present invention, the configuration of the level shifter sections 1, 1 'is not specified, and any configuration requiring an input signal IN and an inverting input signal IN B can be used.
    [88] In addition, by increasing the resistance value of the entire level shift circuit, the normal current value can be maintained at a low level. Therefore, this circuit is particularly effective for a DC system level shifter that does not require an increase in speed.
    [89] As described above, in the level shift circuit according to the present embodiment: the input signal IN and the inverted input signal IN B inverting the high / low of the input signal are input, and at the same time, the high power voltage VHH and the low power supply. A level shifter (1) connected to a voltage VLL and switching VHH and VLL in accordance with the high / low levels of the input signal IN and the inverted input signal IN B; A voltage V HL is applied to give an output level corresponding to the high level of the input signal IN, the power supply voltage VLL, and the inverting input signal IN B, and the high / low of the input signal IN is input. An inverter unit 2 for generating an inverted input signal IN B inverting the input signal IN by switching the output voltage level according to the row; And a voltage divider 3 for dividing and extracting the voltage VHL between the power voltages VHH and VLL.
    [90] When the input signal IN and the inverted input signal IN B inverting the signal are required as the input signal of the level shifter 1, the power supply voltage VHH, which gives high and low levels of the output signal, In addition to VLL, a voltage VHL for providing an output level corresponding to the low or high level of the inverting input signal IN B is required.
    [91] The voltage VHL has conventionally been supplied as a power supply voltage from the outside of the level shift circuit, and thus requires a corresponding terminal. In the above configuration, the voltage VHL is executed by the voltage divider 3. It is generated by the voltage division process at the supply voltages VHH and VLL. For this reason, the terminal for inputting the voltage VHL becomes unnecessary, and the reduction in the number of terminals in the level shift circuit can be realized.
    [92] In the level shift circuit, the voltage divider 3 connects the PMOS transistors P61 to P63 in series between the power supply voltages VHH and VLL and connects them to the gates of the PMOS transistors P61 to P63. The input signal IN can be connected.
    [93] According to the above structure, when the low level input signal IN is input to each gate of the PMOS transistors P61 to P63, these PMOS transistors P61 to P63 are turned on, and in the voltage divider 3 The voltage VHL is extracted by the partial pressure process. In addition, when the input signal IN is at the high level, such a voltage between the gate and the source of each transistor is lower than that at the low level, and the resistance between the source and the drain is high, so that the power source VLL is supplied from the power source VHH. Since the current flowing into the circuit becomes small, the current can be controlled and the power consumption can be reduced.
    [94] Further, in the level shift circuit, the voltage divider 3 may be constituted by a resistor connected in series between the power supply voltages VHH and VLL.
    [95] Further, in the level shift circuit, the semiconductor or the resistor of each transistor which is a component is preferably formed of a polysilicon thin film.
    [96] According to the above structure, in particular, the transistor and the resistor formed in the voltage divider 3 can be formed on the same substrate as the level shifter 1 and the inverter 2. That is, the entire level shift circuit can be formed on the same substrate, and the level shift circuit can be manufactured with a simpler configuration without the need for voltage division using a resistor or the like from the outside. In the case where the voltage divider 3 is formed of a resistor, the layout may be minimized in some cases by disposing the resistor under the wiring pattern by layout.
    [97] In the level shift circuit, the voltage VHL extracted by the voltage divider 3 is a transistor (in this embodiment, the PMOS transistor P13 in which the voltage VHL is a source input in the configuration of FIG. 1). And in the configuration of FIG. 5, it is preferable to set the driving margin at the design threshold of the NMOS transistor N73 in which the voltage VHL is the source input.
    [98] According to the above configuration, since the voltage VHL is set to the intermediate value of the driving margin at the transistor design threshold, even if the threshold value of the transistor in the manufactured level shift circuit deviates from the design value, the set value of the voltage VHL is It is highly likely to exist in the driving margin of the threshold value (including the case of a value shifted from the design value) of the transistor, thereby making it possible to stabilize the operation of the level shift circuit.
    [99] Further, in the level shift circuit, it is preferable that the sum of the resistance values in the voltage divider 3 is set to a larger value within the range of the operable frequency of the level shift circuit.
    [100] According to the arrangement, the sum of the resistance values in the voltage divider 3 is set to a larger value within the range of the operable frequency of the level shift circuit, thereby reducing the current flowing through the voltage dividing means, and thus Low power consumption of the level shift circuit can be realized.
    [101] In addition, in the level shift circuit according to the present embodiment, in response to the input signal IN input from the outside, the inverted input signal IN B, which is the inverted signal, is generated internally to generate a high level of the input signal and the inverted input signal. The output level of the output signal after shifting the input signal level and outputting the signal according to / low, and the voltage VHL giving the high level output level of the inverted input signal lN B is level shifted. It is generated by the resistor division from the power supply voltages VHH and VLL giving.
    [102] When the input signal IN and the inverted input signal IN B are used in the conventional level shift circuit, when the input signal IN and the inverted input signal IN B are externally input in the same manner as the input signal IN, and Two cases are proposed, which are generated internally. When the inverting input signal IN B is externally input, a corresponding input terminal is required in the level shift circuit. Also, in the case where the inverted input signal IN B is generated internally, the high level of the inverted input signal IN B in addition to the power supply voltages VHH and VLL that provide the output level of the output signal after the level shift is applied. Alternatively, a voltage VHL providing an output level of low level is required, and a terminal for supplying the voltage VHL is required.
    [103] In contrast, in the configuration of the level shift circuit according to the present embodiment, the output of the output signal after the voltage VHL providing the output level of the high level (or low level) of the inverting input signal IN B is level shifted. Generated by resistor division from the supply voltages VHH and VLL providing the level. That is, in the level shift circuit, only the terminal for inputting the power supply voltages VHH and VLL providing the output level of the output signal after the level shift is needed, thereby reducing the number of terminals.
    [104] Further, in the level shift circuit, the resistor used in the voltage divider 3 may be formed by, for example, silicon doped with donna or silicon doped with an acceptor.
    [105] In the above level shift circuit, the resistors used in the voltage divider 3 can be formed by connecting NMOS transistors in series and connecting the gate electrode of each transistor to a high power voltage VHH. Alternatively, the PMOS transistors may be connected in series, and the gate electrodes of the transistors may be connected to the low power supply voltage VLL.
    [106] Further, in the level shift circuit, a resistor used in the voltage divider 3 can be formed by connecting NMOS transistors in series and connecting the gate electrode of each transistor to the drain of its own transistor. Alternatively, the PM0S transistors may be connected in series, and the gate electrode of each transistor may be connected to the drain of its own transistor.
    [107] The level shift circuit may be configured to output an output signal OUT having the input signal IN shifted to the positive side, or to output an output signal OUT having the input signal IN shifted to the negative side. have.
    [108] In the level shift circuit, it is preferable to use a thin film transistor as an element constituting the level shift circuit.
    [109] The image display device according to the present embodiment is an active matrix type image display device in which display pixels are arranged in a matrix, and the data signal drive circuit and the scan signal drive circuit have the above level shift circuit.
    [110] That is, in the image display, as shown in Fig. 9, a low voltage control signal is inputted from an input terminal, and the level shift circuit provides a voltage required for the data signal driver circuit and the scan signal driver circuit by the level shift circuit of the present invention. By executing the operation, the image display operation is executed by the data signal driving circuit and the scanning signal driving circuit.
    [111] In the image display apparatus, the number of terminals in the data signal driving circuit and the scanning signal driving circuit can be reduced.
    [112] In the image display apparatus, at least the pixel, the data signal driving circuit and the scanning signal driving circuit are preferably composed of an amorphous silicon thin film, a polycrystalline silicon thin film, or a single crystal silicon thin film.
    [113] While the invention has been described above, it will be apparent that it can be modified in various ways. Such variations are not to be regarded as a departure from the scope and spirit of the invention, and those skilled in the art will recognize that all such modifications are included within the scope of the appended claims.
    权利要求:
    Claims (19)
    [1" claim-type="Currently amended] An input signal and an inverted input signal inverting the high / low of the input signal are input, and are connected to a first voltage, which is a high power voltage, and a second voltage, which is a low power supply voltage, so that the high / low of the input signal and the inverted input signal are high. Level shift means for switching and outputting the first voltage and the second voltage,
    A third voltage is provided to provide an output level corresponding to one of the input signal, one of the first voltage and the second voltage, and a low level or a high level of the inverted input signal, and to a high / low level of the input signal. Inverting input signal generating means for generating an inverting input signal inverting the input signal by switching the output voltage level accordingly; and
    And dividing means for dividing the third voltage between the first and second voltages to extract the third voltage.
    [2" claim-type="Currently amended] 2. The level shift circuit as claimed in claim 1, wherein the voltage dividing means has N channel transistors connected in series between the first and second voltages, and the first voltage is applied to a gate of each N channel transistor.
    [3" claim-type="Currently amended] 2. The level shift circuit as claimed in claim 1, wherein the voltage dividing means has a P-channel transistor connected in series between the first and second voltages, and the second voltage is applied to a gate of each P-channel transistor.
    [4" claim-type="Currently amended] 2. The level shift circuit as claimed in claim 1, wherein the voltage dividing means has N-channel transistors connected in series between the first and second voltages, and drains of the transistors are connected to gates of the respective N-channel transistors.
    [5" claim-type="Currently amended] 2. The level shift circuit as claimed in claim 1, wherein the voltage dividing means has a P-channel transistor connected in series between the first and second voltages, and a drain of the transistor is connected to a gate of each P-channel transistor.
    [6" claim-type="Currently amended] 2. The level shift circuit as set forth in claim 1, wherein said voltage dividing means has a P-channel transistor connected in series between said first and second voltages, and an input signal is connected to a gate of each P-channel transistor.
    [7" claim-type="Currently amended] The level shift circuit according to claim 1, wherein said voltage dividing means is composed of a resistor connected in series between said first and second voltages.
    [8" claim-type="Currently amended] The level shift circuit according to claim 1, wherein the semiconductor of the transistor serving as a component of the level shift circuit is formed of a polysilicon thin film.
    [9" claim-type="Currently amended] 8. The level shift circuit as claimed in claim 7, wherein a resistor serving as a component of the level shift circuit is formed of a polysilicon thin film.
    [10" claim-type="Currently amended] 10. The level shift circuit as set forth in claim 9, wherein said resistor is formed of a polysilicon thin film doped with donna.
    [11" claim-type="Currently amended] 10. The level shift circuit as set forth in claim 9, wherein said resistor is formed of a polysilicon thin film doped with an acceptor.
    [12" claim-type="Currently amended] The level shift circuit according to claim 8 or 9, wherein a third voltage extracted by said voltage dividing means is set within a driving margin of a design threshold of said transistor.
    [13" claim-type="Currently amended] 10. The level shift circuit according to claim 8 or 9, wherein the third voltage extracted by the voltage dividing means is set to an intermediate value of a driving margin of the design threshold of the transistor.
    [14" claim-type="Currently amended] 13. The level shift circuit as set forth in claim 12, wherein the sum of the resistance values in the voltage dividing means is set to a larger value within a range of operable frequencies of the level shift circuit.
    [15" claim-type="Currently amended] The level shift circuit as set forth in claim 13, wherein the sum of the resistance values in the voltage dividing means is set to a larger value within a range of operable frequencies of the level shift circuit.
    [16" claim-type="Currently amended] A level shift circuit that internally generates an inverted input signal, the inverted signal thereof, for an input signal input from the outside, and shifts and outputs an input signal level in accordance with high and low input signals and inverted input signals.
    And a voltage shifting circuit configured to generate a voltage giving a low level or a high level output level of the inverted input signal from the power supply voltage giving the output level of the output signal after the level shifted by resistance division.
    [17" claim-type="Currently amended] An active matrix image display device in which pixels for displaying are provided in a matrix form,
    The data signal driver circuit and the scan signal driver circuit,
    An input signal and an inverted input signal inverting the high / low of the input signal are input, and are connected to a first voltage, which is a high power voltage, and a second voltage, which is a low power supply voltage, so that the high / low voltages of the input signal and the inverted input signal are input. A level shifter means for switching and outputting the first voltage and the second voltage according to the row;
    The input signal, any one of the first voltage and the second voltage, and a third voltage that provides an output level of a low level or a high level of the inverted input signal are input and output according to the high / low of the input signal. Inverting input signal generating means for generating an inverting input signal inverting said input signal by switching a voltage level, and

    And a level shift circuit having a voltage dividing means for dividing the third voltage between the first and second voltages to extract the third voltage.
    [18" claim-type="Currently amended] 18. The image display device according to claim 17, wherein the semiconductor of the transistor which is a component of the level shift circuit is formed of a polysilicon thin film.
    [19" claim-type="Currently amended] 19. The image display device according to claim 18, wherein the third voltage extracted by the voltage dividing means is set to an intermediate value of a driving margin of the design threshold of the transistor.
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    同族专利:
    公开号 | 公开日
    TW523987B|2003-03-11|
    US20010008381A1|2001-07-19|
    US6741230B2|2004-05-25|
    JP2001274676A|2001-10-05|
    KR100405647B1|2003-11-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-01-19|Priority to JP2000-10813
    2000-01-19|Priority to JP2000010813
    2000-11-15|Priority to JP2000-348672
    2000-11-15|Priority to JP2000348672A
    2001-01-18|Application filed by 마찌다 가쯔히꼬, 샤프 가부시키가이샤
    2001-11-14|Publication of KR20010100766A
    2003-11-14|Application granted
    2003-11-14|Publication of KR100405647B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP2000-10813|2000-01-19|
    JP2000010813|2000-01-19|
    JP2000-348672|2000-11-15|
    JP2000348672A|JP2001274676A|2000-01-19|2000-11-15|Level shift circuit and image display device|
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